III B.E. (Computer Engg.)

VIII SEMESTER

8 CP3 COMPUTER AIDED DESIGN FOR VLSI

1.  INTRODUCTION: Why design ICs? Technology and economics for IC manufacturing. COMOS technology -circuit techniques. Power consumption, Design and testability. IC Design Techniques- Hierarchical design, Data abstraction and computer aided design.

2. TRANSISTORS AND LAYOUT:  Fabrication process overview and Fabrication steps. Transistors -Structure. Model and Parasitic, Tub Ties and Latch up. Advanced Transistor characteristics leakage and sub threshold current advanced transistor structure and spice models. Wires and V13S -Wire parasitic and skin effect in copper interconnect. Design Rules -Fabrication Errors. Scalable design rules. SCMOS design rules and typical process parameters. Layout Design and Tools -Layout for Circuit Stick Diagrams, Hierarchical Stick Diagrams. 'Layout Design and Analysis Tools and Automated Layout.

3.    SEQUENTIAL MACHINE: Latches and Rip Hops –Categories of memory elements, Latches and Flip-Flops. Sequential Systems and clocking disciplines -One phase systems for Flip-Hops. Two- phase systems for Latches. Advanced clocking analysis and clock generation. Sequential system Design -structural specification. State Transition Graph. Tables and State assignment. Power optimization. Design validation and sequential testing.

4. SUBSYSTEM DESIGN: Subsystem Design Principles–Pipelining and Data paths. Combinational shifter. Adders ALUs and Multipliers. High Density Memory -ROM. Static RAM. Three- Transistor DRAM and One transistor DRAM.

5.CHIP DESIGN: Design Methodologies. Kitchen Timer chip - Timer specification and Architecture. Architecture Design. Logic design. layout design and Design Validation.

Recommended Books:

1.      Wayne Wolf -Modem VLSI Design. 3.'" ed Pearson Education Asia.

2.      Kiat-Sent Yeo -CMOS/BiCCMOS VLSI. Pearson Education Asia.

3.      Neil H.E. Weste -Principles of CMOS VLSI Design. Pearson Education Asia.